Architecture Examples
An architecture is a design plus the recipe that turns it into a family of configurations: where its sources live, which top level to implement, and which parameters to sweep. The seven examples below are all shipped in a fresh workspace, and all of them run out of the box once an EDA tool is installed.
They are ordered by what they add, not by size. Read the counter first if you want the shortest complete example; read the Cordic if you want to see everything at once.
What these examples demonstrate, together
- Delimiter-based substitution with no markers in the RTL — the existing parameter declaration is the delimiter, so sources stay synthesizable outside Odatix.
- Four RTL languages, plus Chisel and C++ — Verilog, SystemVerilog, VHDL, Scala and a design that only becomes RTL when a generator or a high-level synthesis is run.
- Parameter domains — several parameters swept independently and combined automatically.
- Generated configurations — sweeps described by a variable and a template instead of a directory of files.
- Multi-file designs and synthesis wrappers — packages, submodules, and a top level whose only job is to register the boundary.
- Simulation with several tools — each testbench reporting its own metrics.
Table of Contents
The examples
Cordic (VHDL & SystemVerilog)
A pipelined CORDIC rotation core, described twice, swept over two parameter domains and simulated by four simulators that each report their own accuracy metrics.
Read the example
Counter (4 languages)
The same up/down counter written in Verilog, SystemVerilog, VHDL and Chisel, to show that only the delimiters change — plus a variant parameterized on the command line.
Read the example
ALU (SystemVerilog & Chisel)
A multi-file design with a package, a submodule and a synthesis wrapper — and delimiters that are not unique in the file.
Read the example
Multiplier & Shift Register
Two minimal designs swept over the same widths, one cheap and one expensive, chosen to make the shape of a trade-off curve visible.
Read the example
Sine ROM (Chisel)
A generated sine lookup table swept over address width and data width — two parameter domains whose configurations are themselves generated.
Read the example
Configuration generation
A catalogue architecture that cannot be synthesized: ten settings files, one per way of generating a list of configurations.
Read the example
FIR filter (C++ / Vitis HLS)
A filter written in C++ and turned into RTL by Vitis HLS, sweeping two HLS pragmas and a generation parameter before the design is synthesized like any other.
Read the example
At a glance
| Example | Languages | Parameters | Adds |
|---|---|---|---|
| Cordic | VHDL, SystemVerilog | 2 domains | simulation with four tools, testbench metrics |
| Counter | Verilog, SystemVerilog, VHDL, Chisel | 1 domain | the same sweep in four languages |
| ALU | SystemVerilog, Chisel | 1 domain | multiple source files, synthesis wrapper, ambiguous delimiters |
| Multiplier & Shift Register | SystemVerilog | 1 domain | two designs sharing one set of configuration files |
| Sine ROM | Chisel | 2 domains | generated configurations, formatted names |
| Configuration generation | — | 10 settings files | every variable type, side by side |
| FIR filter (HLS) | C++ | 3 variables | RTL generated by high-level synthesis, pragmas swept from the command line |
Running them
Tutorials
Step-by-step instructions to run the examples, and understand how Odatix works.
Browse the tutorials